A 1.2V 1Mbit embedded MRAM core with folded bit-line array architecture

A 1Mbit MRAM with a 0.81 /spl mu/m/sup 2/ 1-Transistor 1-Magnetic Tunnel Junction (1Tr-1MTJ) cell using 0.13 /spl mu/m 4LM logic technology has been produced. A folded-bitline sensing and common write word-line scheme with dummy row architecture achieves 100MHz random read cycle with n/sup +/ diffusion/Co-silicide read source lines. Employing a distributed gate voltage control scheme, high speed write current switching without write disturb by peak current even at 1.2V power supply is demonstrated.