A 12.5Gbps half-rate CMOS CDR circuit for 10Gbps network applications

This paper describes a true half-rate CMOS CDR circuit suitable for 10Gbps network applications. The CDR adopts a phase detector and a current mode EXOR charge pump with alleviated switching speeds to obtain higher speed margins. A 10.3Gbps CDR for 10Gbps Ethernet has been fabricated using 0.10 /spl mu/m SOI-CMOS process technology. The measured bit error rate of the CDR is less than 10/sup -12/ with a random bit sequence of 2/sup 31/-1. With proposed circuit configuration, the CDR can operate over 12Gbps without error. The jitter tolerance at 10.7Gbps is more than 0.39UIpp with 4M-80MHz jitter frequency range. The input sensitivity is 16mVpp differential. The power dissipation of CDR and 1:2 Deserializer block amounts to 351 mW at a supply voltage of 1.2V.