A 3.3-V 240-MS/s CMOS bandpass /spl Sigma//spl Delta/ modulator using a fast-settling double-sampling SC filter

A bandpass /spl Sigma//spl Delta/ modulator is demonstrated to operate at a very high sampling rate of 240 MS/s by employing a proposed double-sampling switched-capacitor biquadratic filter architecture, which processes with a fast-settling feature. Implemented in a standard 0.35-/spl mu/m CMOS process, the modulator achieves a peak SNDR of 72 dB, 55 dB and 52 dB at a bandwidth of 200 kHz, 1 MHz and 1.25 MHz for GSM, Bluetooth and CDMA2000 applications respectively while dissipating 37 mW and occupying a chip area of 1.2 mm/sup 2/.