Numerical characterization of the stress induced voiding inside via of various Cu/low k interconnects

Modelling methodologies including a dynamic stress evolution are proposed in this work to characterize the relative stress-induced voiding (SIV) probability inside via of various Cu/low k interconnects. Seven patterns being representative of versatile IC design units are selected. It is demonstrated that our modelling approach can serve as a good method identifying the most troublesome layout units to inside-via SIV, and the results aligned well with the experimental data. From our studies, two kinds of layout styles when designed together are found detrimental: (1) the layout units with via(s) subjected to significant upper-metal edge confinement and (2) the one with via close to big vacancy sources.