Novel integrated CMOS sensor circuits

Three novel integrated CMOS active pixel sensor circuits for vertex detector applications have been designed with the goal of increased signal-to-noise ratio and speed. First, a large-area native epitaxial silicon photogate sensor was designed to increase the charge collected per hit pixel and to reduce charge diffusion to neighboring pixels. High charge to voltage conversion is maintained by subsequent charge transfer to a low capacitance readout node. Second, a per-pixel correlated double sampling kT/C reset noise reduction circuit was tested. It requires only one read, as compared to two for typical double sampling in active pixel sensors, and no off-pixel storage or subtraction is needed. The technique reduced input-referred temporal noise by a factor of 2.5 to a measured 15.6 e/sup -/, rms. Finally, a column-level active reset technique was designed that suppresses kT/C reset noise. It reduced noise by up to a factor of 7.6, to an estimated 8.3 input-referred electrons, rms. The technique also dramatically reduces fixed pattern (pedestal) noise, by up to a factor of 21. This may reduce pixel-by-pixel pedestal differences enough to permit sparse data scan without per-pixel offset corrections.