Multilevel placement with circuit schema based clustering in analog IC layouts

We aim at developing an automated device-level placement for analog circuit design which achieves comparable quality to manual designs by experts. It extracts a set of clusters from a circuit schema as experts do. We provide a multilevel placement based on the sequence-pair by relaxing the shape of clusters from rectangles and allowing boundaries of clusters to be 'jagged'. The quality of placement is evaluated by a multiobjective according to an expert's guideline. We adopt a multistep simulated annealing to balance a tradeoff between the objectives. In experiments, we tested the placement for industrial examples. Our tool attained placements better than those by manual on the average by 10.8% and 6.8% with respect to area and net-length, respectively. It also achieved 1/730 layout time compared with the time by manual.