An 80 MHz 10 b pipeline ADC with dynamic range doubling and dynamic reference selection

A 10 b 80 MHz pipeline ADC consumes 22 mA at 1.5 V and occupies a die area of 0.3 mm/sup 2/ in a 0.13 /spl mu/m CMOS technology. The ADC is based on a conventional 1.5 b pipeline architecture combined with dynamic-range-doubling and dynamic-reference-selection algorithms.