A 12 b 80 MS/s pipelined ADC with bootstrapped digital calibration

A 12 b 80 MS/s pipelined ADC is calibrated for constant and signal-dependent gain errors as well as for slew-rate errors. With foreground calibration, peak SNDR is 72.6 dB, and peak SFDR is 85.4 dB. Using an on-chip microprocessor for calibration, the total power dissipation is 755 mW from 2.5 V, and the active area is 19.6 mm/sup 2/ in a 0.25 /spl mu/m CMOS process.