CMOS two-quadrant multiplier using transistor triode regime

A CMOS two-quadrant multiplier using a differential pair with controlled current tail is described. A bias circuit with output current proportional to the square of input voltage provides the tail current for the pair. This bias circuit includes an operational amplifier and two nested transistors. One of these transistors is in pinch-off, the other in the triode region of operation. The transistor mismatch and body effect influence are evaluated. The circuit is verified experimentally.<
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