A novel serial multiplier using floating-gate transistors

The present work introduces a novel family of CMOS latches based on floating gate transistors. The presented logic family carries robustness to fabrication process variation, noise and other problems of the floating gate logics. The robustness of the circuit allows the use of small devices, reducing area requirements. A serial multiplier is implemented to take advantage of those features. The serial approach has been proven to be an efficient implementation for several digital-signal-processing (DSP) structures. A test chip prototype was sent to fabrication using a 0.5 /spl mu/m AMIS CMOS technology. The required area for the serial multiplier was 866/spl times/217 /spl mu/m/sup 2/. A single power supply of 3.3 V was used.