VLSI design of dual-mode Viterbi/turbo decoder for 3GPP

In this paper, a prototype design of a dual-mode Viterbi/turbo decoder for 3rd generation wireless communication systems is proposed. By merging some similar modules in both the Viterbi decoder and the log-MAP turbo code decoder, we built one dual-mode decoder with both of these two functions. When the decoder operates in the turbo mode, early-termination control of the iteration process can reduce the power consumption without influencing the decoding accuracy. Besides, in order to conform to the CDMA2000 standard, our decoder can also perform as a reconfigurable Viterbi decoder. That is, our design meets the requirement of the multi generator polynomial convolutional code specification. The design provides an integrated FEC kernel for modern communication systems.