A novel CMOS double-edge triggered flip-flop for low-power applications

A novel low-power double-edge triggered flip-flop is presented in this paper. Low-power and high-speed flip-flops are required in many applications, especially in SoC systems. Double-edge triggered flip-flop can latch the data signal changes both from high to low and low to high. Thus, lower clock frequency is used while the data throughput is preserved. The proposed flip-flop uses a low-swing clock technology and low-Vt transistors for the clock transistors to reduce the leakage current problem. Beside, only a single latch is used and lower power consumption is achieved. HSPICE simulation results show that the power dissipation of the proposed flip-flop is reduced by at least 28% and the power-delay product is also reduced by at least 50%.