A comparison of graph coloring heuristics for register allocation based on coalescing in interval graphs

Register allocation is an important optimization problem for digital signal processor implementations. Typically, this is modeled as a graph coloring problem for an interference graph. Several heuristics are known but for special classes of interference graphs optimum solutions can be generated. The goal of this paper is to compare different coloring heuristics in order to obtain minimum register requirements. The heuristics are analyzed especially with respect to the performance in case of interval graphs. Control flow and architectural constraints are in conflict with the topology of interval graphs. The number of these constraints has a strong impact on the performance of coloring heuristics. We also show that Chaitin's well known coloring heuristic produces optimum results for interval graphs.