1000BASE-T Gigabit Ethernet baseband DSP IC design

The design of the Gigabit Ethernet baseband DSP IC is based on IEEE standard 802.3ab and focuses on signal processing in 1000BASE-T PHY layer. To achieve the target bit-error rate (BER) of less than 10/sup -10/, the receiver must conquer channel impairments including Inter-Symbol Interference (ISI), Echo, Near-End Cross Talk (NEXT), and Far-End Cross Talk (FEXT). We present low-power, low complexity, and high performance architectures of Echo Canceller, joint Decision Feedback Equalizer, and Trellis Decoder of the baseband DSP receiver in Gigabit Ethernet. The proposed baseband architectures are integrated, co-simulated with the analog front end, and implemented in 2.5 V-0.25 /spl mu/m CMOS standard cell design flow.