A self-synchronized RF-interconnect for 3-dimensional integrated circuits

A self-synchronized RF-interconnect technology (SSRFI), based on capacitor coupling and peak signal detection, is presented in this paper. It can be easily implemented in 3-dimensional ICs (3D-ICs) with small coupling capacitors (60 fF) to interconnect vertical active layers. The demonstrated SSRFI system, including both transmitter and receiver, has been designed, fabricated and verified in UMC 0.18 /spl mu/m CMOS with a verified PRBS (Pseudo Random Binary Sequence) data rate of 3 Gbit/s and a BER (Bit Error Rate) of 1.2/spl times/10/sup -10/. The core circuit burns about 4 mW from a 1.8 V supply and occupies 0.02 mm/sup 2/ chip area.