A linearization technique for RF low noise amplifier

A LNA linearization technique derived from multi-gated configuration using bipolar transistors in CMOS technology is proposed. A bipolar transistor is used to replace the auxiliary MOS transistor to achieve higher operational speed. Both single-ended and differential applications are investigated. Simulation shows that this method is competitive with already reported low noise amplifiers. For 3 GHz of frequency operation, the single-ended structure achieves +15 dBm IIP3 with 8.9 mW power consumption, and the differential architecture can achieve +14 dBm IIP3 with 21 mW power consumption.