A low-power 10-bit continuous-time CMOS /spl Sigma//spl Delta/ A/D converter

This paper presents the design of a third-order low-pass /spl Sigma//spl Delta/ analog-to-digital converter (ADC) employing a continuous-time (CT) loop filter. The loop filter is implemented using G/sub m/ - C integrators, where the transconductors are implemented using CMOS transistors only. System level as well as transistor level design issues for power efficiency is discussed. A prototype /spl Sigma//spl Delta/ ADC intended for weak biological signals restricted to bandwidths below 4 kHz has been manufactured in a standard 0.35 /spl mu/m CMOS technology. The ADC has a measured resolution of 10 bits and a dynamic range (DR) of 67 dB at a sampling rate of f/sub s/ = 1.4 MHz, while drawing a bias current of 60 /spl mu/A from a modest supply voltage of 1.8 V, thus consuming 108 /spl mu/W of power.