Evaluation of a low-cost column bump technology for fine-pitch flip chip and WLP

The use of conventional solder bump for flip chip interconnection is now quite widespread and much infrastructure has been invested in to support this technology. According to the 2003 ITRS roadmap, by 2007, bump pitch of 80 /spl mu/m will be needed. The shrink of bump pitch is driven by migration to 90 /spl mu/m technology. The die to joint gap will also shrink proportionately and start causing problems in underfill flow as well as increase stress on the fragile low-k dielectrics on die face. Tin capped gold column bumps were developed over a decade ago for fine pitch (50 /spl mu/m) flip chip interconnection of gallium arsenide power amplifiers used in mobile phones. Similar technology has now been developed for silicon applications using solder capped nickel column bumps deposited over various under bump metallurgies. By varying the deposition process, bump columns and solder caps of several diameter (50 to 100 /spl mu/m), aspect ratio and heights (5 to 40 /spl mu/m) were deposited. Two solder compositions, eutectic Pb-Sn for baseline and Sn-Ag-Cu were used. Bonding processes were varied to create both barrel and fillet-shaped flip chip joints to organic boards. Stress distribution in flip chip joints of various geometries were estimated by modeling and extended to lifetime prediction. The test assemblies were stressed by thermal cycling and high temperature hold. In this paper, the results of the ongoing reliability tests and a cost estimate for this new low-cost bump technology that addresses many of the shortcomings of the now standard solder bump technology will be discussed.