Underfill for low-k silicon technology

The trend towards copper metallization and low-k dielectrics for 0.13/spl mu/m (and beyond) silicon technologies is driving the development of new packaging processes and materials. In flip-chip packages, the most critical material is the underfill material. Due to its close proximity to the inner layers of silicon die, the underfill material influences the stress conditions at the low-k layers of the silicon. Hence, the underfill material and its associated processes play a big role in determining the reliability of the silicon in the flipchip package. New underfill materials have been recently developed to minimize the die stress and prevent inner layer delamination in silicon while concurrently reducing the strains on the flipchip solder joints. This paper discusses some of the key process and material issues encountered in the development of underfill materials for low-k applications at LSI Logic and Henkel Loctite Corp. In addition, the paper describes the material selection and process optimization methodologies that were followed in the process development work.