A low-power highly-digitized receiver for 2.4-GHz-band GFSK applications

This paper describes the design and measurement results of a low-power highly-digitized receiver for GFSK-modulated input signals at 2.4 GHz. The RF front-end is based on a low-IF architecture and does not require any variable-gain or filtering blocks. The full dynamic range of the low-IF signal is converted into the digital domain by a low-power high-resolution time-continuous /spl Sigma//spl Delta/ ADC. This leads to a linear receive chain without limiters. The digital block performs channel filtering and demodulation. The high degree of digitization leads to design flexibility with respect to changing standards and scalability in future CMOS generations. The receiver has been realized in a standard 0.18-/spl mu/m CMOS process and measures 3.5 mm/sup 2/. The only external components are an antenna filter and a crystal. The power consumption is only 32 mW, which is at least a factor of two lower than state-of-the-art CMOS receivers.