Fabrication and parametric study of wafer-level multiple-copper-column interconnect

Electronic packaging technology lags behind the rapidly developing semiconductor technology, and as a result the package has become the limiting factor for microsystem performance. A critical aspect of package performance is the reliability of chip-to-next-level interconnects. This paper presents some initial fabrication and simulation results of a compliant interconnect scheme, which features multiple copper columns in a single interconnect and is expected to demonstrate high thermomechanical reliability as predicted by a simplified model. Prototype interconnects with pitch of 40 /spl mu/m have been realized based on wafer-level processes such as photolithography and electrolytic plating. Simulation tools such as Ansys and Ansoft's Q3D are employed to compare mechanical and electrical performance of multi-copper-column (MCC) and single-copper-column (SCC) interconnect that has been available in the market. Parametric studies are implemented to investigate the geometric effects of MCC interconnects on their performances.