On the evaluation of SEU sensitiveness in SRAM-based FPGAs

The growing adoption of SRAM-based field programmable gate arrays (FPGAs) in safety-critical applications demands for efficient methodologies for evaluating their reliability. Single event upsets (SEUs) affecting the configuration memory of SRAM-based FPGAs are a major concern, since they can permanently affect the function implemented by the device. We exploited a fault-injection environment developed at our institution to analyze the impact of such faults on SRAM-based FPGAs when fault tolerant design techniques are adopted. The experimental results allow quantitative evaluations of the effects of these faults, and show that the sensitivity of the TMR design technique mainly depends on the characteristics of the adopted TMR architecture in terms of placing and routing.