A hierarchical self test scheme for SoCs

Complex systems on a chip (SoCs) suffer from a couple of test related problems. In almost any case they contain processor devices and complex on-chip networks that need to be tested under heavily restricted access from the outside. Today multi-processor SoCs (MP-SoCs) are becoming the rule rather than the exception and many SoCs consist of heterogeneous multi-processor networks that are partly asynchronous. Therefore, testing processor structures (logic, busses, memory) is an essential part of the problem. For SoCs in safety-critical applications, self-test functions that work independently from external tester devices are becoming a must. This paper presents a new concept for a tester-independent "bottom up" self-test strategy for multi-processor SoCs.