Thermal modeling of a small extreme power density macro on a high power density microprocessor chip in the presence of realistic packaging and interconnect structures

By utilizing a lumped-multilayer-based method, we have studied the thermal behavior of a generalized rectangular macro with an extremely high power density of 2500 W/cm/sup 2/ on a microprocessor chip of average power density 40 W/cm/sup 2/. We consider both conventional bulk Si CMOS technology and silicon on insulator (SOI) CMOS. Practical features, including the presence of realistic packaging and interconnect structures are thoroughly analyzed. We found that the worst case temperature rise for such a hotspot is about 11% (/spl sim/7/spl deg/C) above the global chip temperature rise (/spl sim/80/spl deg/C) for 2500 W/cm/sup 2/ power density in SOI technology. As a result of the presence of buried oxide, the thermal behavior of a 15/spl times/300 /spl mu/m/sup 2/ macro in bulk technology is significantly different from SOI technology. It is also found that the existence of the interconnect layers and a solder ball optimally positioned right above the heated macro enables the heat flow to spread horizontally above the macro before eventually being dissipated downwardly toward the heat sink, thus decreasing the peak temperature rise of the macro in the device plane.