Failure analysis for bumped-die device cratering via finite element modeling

This paper presents a case-study result showing how finite element modeling can assist investigation of stress-related failure in electronic components. The package in discussion is a very specific type of flip chips (bumped die). Driven by customer's requirements, it is designed with extra-large solder bumps, and to be surface-mounted on organic PCB (Printed Circuit Boards) with no underfill. It was found that for certain bump designs, the units are prone to fail during the temperature cycle test as a result of device cratering. Mechanics of the reliability failure is somewhat subtle. Finite element modeling was undertaken to assess stress in the solder bump. It turned out that initial modeling results showed dramatic discrepancy from test results. Having thoroughly checked the solution, particularly as various modeling approaches generated consistent results, it was then led to suspicion that micro-damages might have occurred in the package. In other words, the initial model without including any defect only represents pristine units, and is no longer adequate in representing tested samples. Subsequent bump pull test and fractography analysis did find undetected debonding at BCB/passivation interface in solder bumps. Analysis results from updated delamination-included model correlated with test data perfectly, confirming that the device cratering is end result of preceding delamination in the flip chip.