Effect of magnetic field on plasma damage during VIA etching in sub-micron CMOS technology

The impact of VIA etching process with magnetic field and main etch time on plasma damage to gate oxide of n/pMOS capacitors has been intensively investigated. It is reported that the lower magnetic field during VIA etching process can reduce the plasma charging damage to the gate oxide. The magnetic field and main etch time at VIA etching are dominant factors to reduce the plasma charging damage.