Local redesign for reliability of CMOS digital circuits under device degradation

More and more attention has been paid to the study of major failure mechanisms such as hot-carrier, gate oxide wear-out, and electromigration, the modeling; and simulation of their impacts on circuit degradation, even design approaches specifically for releasing circuit wear-out degradation. IC reliability simulator ARET (ASIC Reliability Evaluation Tool), developed at Georgia Institute of Technology is able to simulate circuit-level reliability under hot-carrier and electromigration. One distinct achievement of ARET is its application in design-for-reliability (DFR). DFR was introduced in practical IC development cycle by adding a reliability simulation phase before circuit fabrication. Thus, the reliability problem can be identified and possibly fixed by circuit re-design before actual manufacture. In ARET the reliability hotspot identification function was accomplished specifically to facilitate DFR. Based on the identification of reliability hotspot, which is the circuit component most likely to fail the whole circuit, the concept of local design-for-reliability (LDFR) is proposed. In LDFR, only the design around the reliability hotspot area needs to be updated and the design work involved is thus much simplified and reduced, which makes LDFR a practically feasible DFR approach. Upon a successful LDFR, the overall circuit reliability can be significantly improved, while the expected performance specifications in the original design are still maintained.