Charge trapping and device performance degradation in MOCVD hafnium-based gate dielectric stack structures

Electron trapping data obtained with the pulsed I/sub d/-V/sub g/ measurement suggests that the trapping effectively occurs in the bulk of the high-k film rather than only at the interface of the high-k dielectric and interfacial oxide. This leads to less trapping in physically thinner high-k gate stacks. Carrier mobility of thinner hybrid stacks corrected for the inversion charge loss due to electron trapping is found to be approaching the universal high field electron mobility.