Impact of gate sidewall spacer structures on DRAM cell transistors under Fowler-Nordheim and gate-induced drain leakage stress conditions

We studied the reliability characteristics of cell transistors with two-different type gate sidewall spacer structures (O/N vs. N/O/N) in terms of Fowler-Nordheim (F-N) or gate-induced drain leakage (GIDL) stress-immunity. Through gate oxide stress-induced leakage current (SILC), junction leakage, GIDL, and drain current-gate voltage (Id-Vg) measurement, it was observed that the GIDL stress condition had much more critical effects on the reliability of cell array transistors than the F-N stress. Particularly, it was also found that the GIDL stress-induced device degradation was severer in case of the N/O/N gate sidewall spacer than the O/N spacer. It is thought that the relatively poor reliability of the N/O/N is closely related to the trap generation near the interface of the re-oxidized SiO/sub 2//nitride at the gate bottom edge as well as the defect generation due to the sidewall nitride film stress.