Effects of hot spot hopping and drain ballasting in integrated vertical DMOS devices under TLP stress

The effects of hot spot hopping and drain ballasting are investigated in vertical DMOS devices under ESD stress. The frequency of the hot spot hopping between two neighboring channels of the device is shown to be dependent on the dose of the n-type buried layer (BLN). A correlation between the hopping frequency and the maximum average temperature of the device and hence its robustness under transmission line pulsing (TLP) testing, is found. The devices are analyzed using on-wafer TLP measurements and backside transient interferometric mapping experiments.