Investigation of circuit-level oxide degradation and its effect on CMOS inverter operation and MOSFET characteristics

Circuit-level oxide degradation effects on CMOS inverter circuit operation and individual MOSFET behavior is investigated. Individual PMOSFET and NMOSFET devices are assembled off-wafer in the inverter configuration through a switch matrix. A range of gate oxide degradation mechanisms are induced by applying a ramped voltage stress (RVS) of various magnitudes to the input of the inverter. A novel circuit model is used to simulate the voltage transfer curves (VTCs) of degraded inverters. At the transistor level, increased gate leakage currents of nearly eight orders of magnitude are observed, in addition to severely reduced on-currents (> 50 percent reduction), and large threshold voltage (V/sub th/) shifts (> 100 mV). At the circuit-level, stress of either polarity results in inverter performance degradation. For the DC characteristics, oxide degradation attributed to limited hard breakdown (LHBD) in the NMOSFET and hard breakdown (HBD) in the PMOSFET, results in decreased output voltage swing (> 260 mV). Under the same conditions, inverter degradation in the voltage-time (V-t) domain exposes much larger changes in performance. For instance, significant increase in the rise time results in the output voltage being pulled up to only 660 MV (V/sub DD/ = 1.8 V) before switching low. From a circuit reliability viewpoint, it may be possible for subsequent circuit stages to compensate for a few degraded devices, but in highspeed circuits, increased rise/fall and delay times may cause timing issues. Furthermore, increased gate or off-state leakage currents can potentially load previous circuit stages or result in increased power consumption.