Impact of stress induced leakage current on power-consumption in ultra-thin gate oxides

A systematic study of the impact of stress-induced-leakage-current (SILC) on chip reliability in terms of power-consumption is presented for the first time. The lognormal distribution is shown to be preferred over the Weibull distribution for the description of the statistics of the time to failure due to SILC-related power consumption increase (T/sub SILC/). The dependences of T/sub SILC/ statistics on various factors such as area, temperature and voltage are explored and reported. Moreover, a methodology is developed to provide reliability assessments and projections for a wide range of ultra-thin oxides down to 1.0nm. It is shown that power-consumption due to SILC increase will not be a limiting factor for ultra-thin gate oxides.