Impact of gate-leakage currents on CMOS circuit performance

Ultra-thin gate dielectrics are exploited in fabrication of MOSFET's featuring channel lengths in the decananometer range: the ITRS indicates that oxide thickness in the order of 1 nm will be used in 2005 for ultra-short CMOS. For such aggressively scaled devices, gate-leakage currents represent a critical issue. In this paper, a study on the impact of Direct-Tunneling (DT) current on the behaviour of a wide variety of CMOS circuits is presented, based on a simulation strategy aimed at predicting the correlation of major performance indices with oxide thickness.