Wafer-level 3D manufacturing issues for streaming video processors

The performance of both 2D and 3D implementations of a streaming video processor is presented incorporating 130 nm technology node parameters. The reduced memory access time predicted for the 4 MB L2 cache (0.9 ns for 3D and 1.65 ns for 2D) is indicative of performance advantages projected for 3D implementations of memory-intensive architectures.