Accuracy improvement of the "Single Pattern Driver" method for the characterization of interconnect capacitance in the context of nanometer technology development

Characterization, modelling and monitoring of interconnect capacitance are of first interest for CMOS and BiCMOS technology development, especially for circuit delay evaluation. An improvement of the Single Pattern Driver method is proposed in this paper to take into account MOST intrinsic and diode leakages which can introduce errors of the order of few hundred aF in advanced nanometer technologies. The accuracy is hugely improved and reaches now 10aF.