A 75 MHz CMOS digital convolver

A dynamic logic digital convolver utilizing a 1- mu m commercial CMOS process has been developed. The convolver is a linear systolic array with a time-bandwidth product of 1024 and a processing gain of nearly 30 dB. It features a single-phase clock with dynamic D flip-flops as the basic storage elements. The device, in a four-chip set, acts as a matched filter which is intended to compare a noise-like signal against a reference signal. The input buffers incorporate ESD protection diodes and convert TTL to CMOS levels. The output buffers use transistors sized to drive 20-pF loads with CMOS levels (TTL-compatible) signals with rise and fall times of less than 1 ns. Design and performance of the convolver are determined.<
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