The hierarchical HDL-based design of an integrated MEMS-CMOS oscillator

A hierarchical and mixed-domain design approach is implemented within the Cadence/sup /spl reg// simulation framework and applied to an integrated MEMS-CMOS oscillator. Parameters concerning both the electronic circuit description at transistor level and the MEMS structure defined by its topology and dimensions, are available during simulation. This approach can lead to a full optimisation of the complete MEMS-CMOS sub-system, with a view to both electrical and mechanical specifications.