A charge-control SPICE engineering model for the parasitic bipolar transistor action in SOI CMOS single-event upsets

An ion strike on an SOI CMOS transistor produces a charge cloud of electron-hole pairs. The subsequent behavior of the charge cloud as it spreads and impinges on the source and drain junctions is explained by 1-D analytical solutions and by 2-D device simulations. By examining the charge cloud from a "top view" perspective and a "side view" perspective, it is shown that a 2-D "side view" simulation gives about the same electrical behavior as would a 3-D simulation, thereby eliminating the necessity for expensive and time-consuming 3-D simulations. It is further shown that the electrical behavior predicted by 2-D simulations can be captured in a simple bipolar SPICE model, which is necessary for practical SEU analysis of large numbers of logic and memory cell types. The SPICE model is based on fundamental physical parameters, not curve-fitting. The predictions of the SPICE model correlate well with experimental SEU sensitivities of a D-type flip-flop and a six-transistor SRAM cell processed in a 0.35 /spl mu/m SOI technology.