Development of a verification method for timed function blocks using ESDT and SMV

As programmable logic controllers (PLCs) are widely used in the digital instrumentation and control (I&C) systems of nuclear power plants (NPPs), the safety of PLC software has become the most important consideration. In this work, we propose a method to perform effective verification activities on the traceability analysis and the software design evaluation in the software design phase. In order to perform the traceability analysis between software requirement specification (SRS) written in a natural language and software design specification (SDS) written in function block diagram (FBD), this method uses extended- structured decision table (ESDT). ESDTs include information related to the traceability analysis from SRS and SDS, respectively. Through comparing with two ESDTs, an effective traceability analysis can be achieved. For the software design evaluation, we use model checking as a formal verification method. FBD-style design specification is translated into symbolic model verifier (SMV) input language and then the FBD-style design specification can be formally analyzed using SMV model checker.