Planarization for 0.5 mu m CMOS/BiCMOS technology

An all-SOG (spin-on glass) planarization process is proposed for 0.5- mu m VLSI technology. The limited depth-of-focus of advanced lithography demands good planarization for both under-metal and inter-metal dielectric layers. A silicate SOG-based process was characterized for interpoly and poly-to-metal planarization, and a siloxane SOG-based process was characterized for inter-metal planarization. The poisoned via problem was solved by using a selective CVD W process for via filling. The specific via resistance is lower than 2*10/sup -8/ Omega -cm/sup 2/ with a good yield (no failure for 240000 vias).<
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