A high performance, four metal layer interconnect system for bipolar and BiCMOS circuits

Two similar four-layer metal systems have been developed to meet the requirements of MOSAIC IV and V high-performance bipolar and BiCMOS circuits. These systems have planarized surfaces obtained using an n-layer photoresist and etchback processes with PETEOS as an interlayer dielectric (ILD). The high-aspect-ratio vias are filled with a multistep hot sputtered Al process. CVD W is also being evaluated as a via fill process. The initial design rules were based on the circuit goals, performance modeling, process and material capabilities, and reliability goals. The development of these processes and the design rule selection process are discussed. Test vehicles were built, and the processes and modeling were verified. Results from the test vehicles as well as a MOSAIC IV demonstration circuit are presented.<
>