Efficient improvement of hot carrier-induced degradation for 0.1-/spl mu/m indium-halo nMOSFET

The effect of post-thermal annealing after indium-halo implantation on the reliability of sub-0.1-/spl mu/m nMOSFETs was investigated. We found that the control of annealing time is more efficient than that of annealing temperature with respect to improving the hot carrier-induced device degradation. The best results of device performance were obtained with post-annealing treatment performed at medium temperatures (e.g., 900/spl deg/C) for a longer time.