Electrical modelling of LSCRs in deep submicron CMOS technologies for circuit-level simulation of ESD protection structures

This paper presents an electrical model of a parasitic LSCR that represents the inner currents before and after triggering. It relies on the standard LSCR model before triggering, and on a PiN diode model for the post-triggering behaviour. As an illustration, the model has been validated against silicon in both 0.18/spl mu/m and 0.13/spl mu/m technologies.