VHDL based design of an FDWT processor

This paper presents the hardware design of a forward discrete wavelet transform (FDWT) processor using VHDL. The design is based on the JPEG2000 standard and utilises the lossless features of FDWT. This is a reversible algorithm, which means there is no loss of information while compressing and transmitting the image information. This paper presents the hardware architecture of the processor as well ns the design of its constituent components in VHDL. The architecture does not comprise any hardware multiplier unit and therefore suitable for development of high-performance image processors. Simulations show that one block of an image can be transformed up to 5 levels of computation using this FDWT processor.