A novel W/WNx/dual-gate CMOS technology for future high-speed DRAM having enhanced retention time and reliability

This work describes a new DRAM cell technology, W/WNx/P/sup +/-gate NMOS memory cell (MC) transistors, which has been integrated into a dual-gate CMOS process. Operation speed, data retention time (t/sub REF/), and reliability of high speed DRAMs are dramatically improved by the P/sup +/-gate NMOS cell, having a low-resistance polymetal word line (WL). Transistor performance in the periphery circuit is enhanced by dual-gate CMOSFETs formed with a low temperature process. These technologies offer excellent scalability and fully operating DDR-II SDRAM test chips have been obtained.