Performance improvement of MOSFET with HfO/sub 2/-Al/sub 2/O/sub 3/ laminate gate dielectric and CVD-TaN metal gate deposited by TAIMATA

For the first time, we integrated a HfO/sub 2/-Al/sub 2/O/sub 3/ laminate gate dielectric with a CVD-TaN metal gate deposited by TAIMATA (tertiaryamylimidotris dimethylamidotantalum) in n/pMOSFETs. It was found that TaN films with low impurity contents were required for optimized capacitance. Together with a slight improvement of the transconductance and a substantial gain in inversion EOT with HfAlO/TaN, improved current drivability was observed in comparison to nitrided-SiO/sub 2//poly-Si and HfAlON/poly-Si with similar EOTs. In addition, CVD-TaN resulted in improved J/sub g/ characteristics, showing F-N tunneling behavior with an effective barrier height of 1.1 eV in nMOS in the inversion region. These results suggest that a CVD-TaN metal gate is necessary for the implementation and scaling of high-k gate dielectrics.