A pulsed sensing scheme with a limited bit-line swing

A pulsed sensing scheme with a limited bit-line swing designed for 4-Mb CMOS high-speed DRAMs (HSDRAMs) and beyond is presented. It uses a standard CMOS cross-coupled sense amplifier and limits the swing by means of a pulsed sense clock. The signal loss that would occur if the bit-line swing were not exactly limited to one threshold above the word-line's low level is avoided by using a small reference voltage generator and trench decoupling capacitors. The sensing scheme was successfully implemented on an experimental HSDRAM fabricated by using 0.7- mu m L/sub eff/ CMOS technology, and a high-speed random access time of 15 ns and a low power dissipation of 144 mW were obtained for 512-kb array activation with a fast cycle time of 60 ns at 3.6 V.<
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