Modelling impact of digital substrate noise on embedded regenerative comparators

This paper presents an analysis and high-level modelling method used to estimate the impact of digital substrate noise on a CMOS regenerative comparator embedded in a mixed-signal environment. A test chip was designed in a 0.35 /spl mu/m heavily doped substrate technology in order to measure the impact of digital noise on embedded CMOS regenerative comparators. Secondly an efficient equation-based model of the impact of the digital substrate noise on embedded CMOS regenerative comparators was derived. It is based on the statistical analysis of the jitter measured at the output of the comparator.