Influence of junction capacitance on SRAM SEU performance [MOSFETs]

Source and drain junction capacitance has been varied by utilizing different implant conditions for the MOSFETs to explore the possibility of improving SEU (single event upset) immunity of SRAM cells. It is found. that the junction capacitances of both the n/sup +//p-well and p/sup +//n-well can vary in a wide range. The resulting SEU FIT (failure in time) rate shows a significant reduction. HSPICE simulation indicates that critical charge of the SRAM cell increases by 5%. The reduction of funnel length due to the higher doping concentration in the source/drain area also improves SEU immunity.