Gate isolation technology for compact poly-CMP embedded flash memories

Downscaling the cell size of embedded flash memories is hampered by a minimum thickness of the tunnel oxide due to reliability constraints. The longer effective channel of the compact poly-CMP flash cell is beneficial for its scalability compared to a discrete two-transistor cell. This paper investigates the influence of the isolation spacer between the floating and access gates in the compact poly-CMP cell on read and leakage currents, programming and erasing characteristics and endurance. The effect of sidewall oxidation steps on the read current of the compact cell is also analysed. This has led to an improved scalable embedded compact poly-CMP flash cell aimed for the 90 nm CMOS generation and beyond.